Neural networks (NNs) for real-time medical image processing in resource-constrained environments benefit from hardware platforms that ensure deterministic timing, low latency, and fine-grained control over computational resources. This work introduces a fully custom and modular hardware framework for implementing fully connected neural networks (FCNs) on FPGAs, targeting online quantitative MR fingerprinting (MRF) reconstruction without relying on high-level synthesis tools. The proposed approach is based on a reusable base node that integrates numerical operations within a compact, parameterizable hardware unit. A single block of 16 such nodes is instantiated and reused in time multiplexing over a fixed schedule, so that the number of clock cycles of an inference is a property of the design rather than of the data. The framework is validated through a three-way comparison: the proposed custom accelerator, three hls4ml-generated designs, and the reference software implementation. The complete network was executed on an AMD/Xilinx Alveo U250 board over a 5000-sample dataset covering a broad range of (Formula presented.) and (Formula presented.) values: the accelerator agrees with the reference 8-bit quantized model on every one of the integer outputs, so that the residual error of the deployed system, a mean absolute percentage error (MAPE) of (Formula presented.) on (Formula presented.) and (Formula presented.) on (Formula presented.) with respect to the ground truth, is entirely that of the quantized network and not of the hardware. Timing closure at (Formula presented.) MHz and post-implementation analysis indicate a (Formula presented.) speed-up over CPU execution, and an estimated energy reduction of (Formula presented.), with limited FPGA resource usage and approximately (Formula presented.) W power consumption. None of the three hls4ml configurations tested reached a working bitstream on the target device, while the proposed architecture completed place-and-route and was executed on hardware, supporting its use as a building block for online quantitative MRI reconstruction.
Ricchi, M., Alfonsi, F., Barbieri, M., Retico, A., Gabrielli, A., Brizi, L., et al. (2026). A Modular VHDL Framework for Deterministic FPGA Acceleration of MR Fingerprinting Reconstruction. APPLIED SCIENCES, 16(19), 1-23 [10.3390/app16199935].
A Modular VHDL Framework for Deterministic FPGA Acceleration of MR Fingerprinting Reconstruction
Ricchi, Mattia;Alfonsi, Fabrizio;Gabrielli, Alessandro
;Brizi, Leonardo;Testa, Claudia
2026
Abstract
Neural networks (NNs) for real-time medical image processing in resource-constrained environments benefit from hardware platforms that ensure deterministic timing, low latency, and fine-grained control over computational resources. This work introduces a fully custom and modular hardware framework for implementing fully connected neural networks (FCNs) on FPGAs, targeting online quantitative MR fingerprinting (MRF) reconstruction without relying on high-level synthesis tools. The proposed approach is based on a reusable base node that integrates numerical operations within a compact, parameterizable hardware unit. A single block of 16 such nodes is instantiated and reused in time multiplexing over a fixed schedule, so that the number of clock cycles of an inference is a property of the design rather than of the data. The framework is validated through a three-way comparison: the proposed custom accelerator, three hls4ml-generated designs, and the reference software implementation. The complete network was executed on an AMD/Xilinx Alveo U250 board over a 5000-sample dataset covering a broad range of (Formula presented.) and (Formula presented.) values: the accelerator agrees with the reference 8-bit quantized model on every one of the integer outputs, so that the residual error of the deployed system, a mean absolute percentage error (MAPE) of (Formula presented.) on (Formula presented.) and (Formula presented.) on (Formula presented.) with respect to the ground truth, is entirely that of the quantized network and not of the hardware. Timing closure at (Formula presented.) MHz and post-implementation analysis indicate a (Formula presented.) speed-up over CPU execution, and an estimated energy reduction of (Formula presented.), with limited FPGA resource usage and approximately (Formula presented.) W power consumption. None of the three hls4ml configurations tested reached a working bitstream on the target device, while the proposed architecture completed place-and-route and was executed on hardware, supporting its use as a building block for online quantitative MRI reconstruction.| File | Dimensione | Formato | |
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