Analysis and Mitigation of Cells Programming Misalignments in PCM-based AiMC Cores

Analog in-Memory Computing (AiMC) based on Phase-change Memory (PCM) enables highly efficient Ma-trix-vector Multiplication (MVM) for edge-AI workloads. However, sequential programming of PCM cells introduces timedependent conductance misalignments that may degrade computational accuracy, especially in large arrays. This work analyzes the impact of programming delay-induced errors in PCM-based AiMC systems. An analytical model is derived to characterize the resulting MVM error as a function of array size, programming time, and drift coefficients. Then, two mitigation techniques are proposed to mitigate the MVM error, namely Importance-Aware Scheduling (IAS) and Digital Rescale Compensation (DRC). These approaches are experimentally validated on a 512×512 PCM-based AiMC prototype, achieving up to 85% reduction of MVM error induced by the programming scheme.