Superconducting Fault Current Limiters (SFCLs) have reached a mature Technology Readiness Level, making their deployment in power grids increasingly relevant. While applications in AC networks are well studied, HVDC grids pose distinct challenges due to different fault dynamics and the reliance on Modular Multilevel Converters (MMCs). This work develops a mathematical model of a simplified DC grid including an SFCL based on High-Temperature Superconducting (HTS) tapes and an MMC represented by an Averaged Value Model (AVM). The model couples network and converter dynamics with the nonlinear temperature- and current-dependent properties of the SFCL, enabling efficient parametric studies under fault conditions. The analysis investigates key design parameters, such as the HTS tape length, highlighting their influence on SFCL and grid performance and providing guidelines for optimal device design.
Bocchi, M., Musso, A., Angeli, G., Morandi, A., Simonazzi, M., Guerra, E., et al. (2026). A Simplified Model for the Conceptual Design of SFCLs in MMC-Based HVDC Grids. IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 36(5), 1-6 [10.1109/TASC.2026.3652516].
A Simplified Model for the Conceptual Design of SFCLs in MMC-Based HVDC Grids
Morandi A.;Simonazzi M.;Guerra E.;
2026
Abstract
Superconducting Fault Current Limiters (SFCLs) have reached a mature Technology Readiness Level, making their deployment in power grids increasingly relevant. While applications in AC networks are well studied, HVDC grids pose distinct challenges due to different fault dynamics and the reliance on Modular Multilevel Converters (MMCs). This work develops a mathematical model of a simplified DC grid including an SFCL based on High-Temperature Superconducting (HTS) tapes and an MMC represented by an Averaged Value Model (AVM). The model couples network and converter dynamics with the nonlinear temperature- and current-dependent properties of the SFCL, enabling efficient parametric studies under fault conditions. The analysis investigates key design parameters, such as the HTS tape length, highlighting their influence on SFCL and grid performance and providing guidelines for optimal device design.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
