The goal of the SINPLEX project is to develop an innovative solution to significantly reduce the mass of the navigation subsystem for exploration missions which include landing and/or rendezvous and capture phases. The system mass is reduced while still maintaining good navigation performance as compared to a conventional modular system. This is done by functionally integrating the navigation sensors, using micro- and nanotechnology to miniaturize electronics and fusing the sensor data within a navigation filter to improve navigation performance. A breadboard system was build including a navigation computer, IMU, laser altimeter/range finder, star tracker and navigation camera and has space for the redundant counterparts. Testing using the TRON hardware-inthe- loop testbench is ongoing. This aper covers some key design properties of the built system and presents some initial performance results of the hardware- in-the-loop tests.
Steffes, S., Dumke, M., Heise, D., Sagliano, M., Samaan, M., Theil, S., et al. (2014). Target relative navigation results from hardware-in-the-loop tests using the sinplex navigation system. Univelt Inc..
Target relative navigation results from hardware-in-the-loop tests using the sinplex navigation system
Sagliano M.;
2014
Abstract
The goal of the SINPLEX project is to develop an innovative solution to significantly reduce the mass of the navigation subsystem for exploration missions which include landing and/or rendezvous and capture phases. The system mass is reduced while still maintaining good navigation performance as compared to a conventional modular system. This is done by functionally integrating the navigation sensors, using micro- and nanotechnology to miniaturize electronics and fusing the sensor data within a navigation filter to improve navigation performance. A breadboard system was build including a navigation computer, IMU, laser altimeter/range finder, star tracker and navigation camera and has space for the redundant counterparts. Testing using the TRON hardware-inthe- loop testbench is ongoing. This aper covers some key design properties of the built system and presents some initial performance results of the hardware- in-the-loop tests.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.



