Readout Architectures and Efficiency for Large Matrix of Pixels

Pixel device systems are now again under investigation for applications in future High-Energy Physics (HEP) experiments or in upgrade of current colliders, like Super-Large Hadron Collider (SLHC). The increase of luminosity and, consequently, the amount of data to be read out forces the pixel detectors into gaining on-chip fast readout electronics. This in fact, can significantly increase the overall performance of the system. Innovative solutions are deemed particularly useful for large, low-pitch pixel circuits that implement huge pixel connectivity via very large control and data buses. The idea is to have a small simple structure that may be expanded to large matrices of pixels without affecting layout complexity and maintaining a reasonably high readout speed. In addition, routing between the sensors can produce false hits, due to induced noise. Hence this chapter proposes to use only inter-pixel global wires and not point-to-point wires from the border of the matrix to single pixels or groups of pixels (global wires only). The approach sets out to simplify inter-pixel routing by moving registers and sparsification logic outside the matrix within a less congested and less critical area. The columns of pixels are read out one at a time and all hits belonging to the same column are read in parallel and independently of the number of the rows and columns not containing hits, which are ignored. In principle, the entire readout phase takes as many clock periods as the number of columns that have hits. It follows therefore that the readout speed might be significantly reduced with respect to that of recently used pixel detectors where a token-like technique is implemented. Additionally, as in normal practice, each matrix sweep cycle is associated with a time-stamp to reconstruct the hits according to the time they were produced. For this the columns activated within the same event are frozen until they are read out. As the pixel logic does not require any internal register, time-stamps can be saved outside the matrix of pixels within a less congested area. In conclusion, the solution features inter-pixel wiring independent of the size of the matrix since there are no point-to-point wires; all lines are global. This readout approach can easily be extended to any size matrix, as it is independent of the number of pixels. This chapter proposes readout architectures for pixel devices where traditional, insufficiently fast structures, such as token-passing techniques, cannot fulfill speed requirements. For low-occupancy devices, this technique should be considered for its simplicity as it could also be used in future improvements in the electronics of physics experiments.