The need to assist the NoC-based Multi-Core Design via System-level open Tools is demonstrated by the amount of research in the design space exploration of networks on chip (NoC) and in the need for preliminary performance evaluation of metrics, application mapping and scalability issues. This chapter provides a detailed analysis of innovative research solutions for characterization of Synthetic Traffic Models, Graph Theoretical Analysis, methodologies for Task Mapping for System on Chip (SoC) Applications, illustration of the potential of the OMNeT++ Simulation Framework and a case study illustration of all those solutions integrated for the study of the STM Spidergon NoC architecture.

System-Level Tools for NoC-Based Multi-Core Design

BONONI, LUCIANO;
2010

Abstract

The need to assist the NoC-based Multi-Core Design via System-level open Tools is demonstrated by the amount of research in the design space exploration of networks on chip (NoC) and in the need for preliminary performance evaluation of metrics, application mapping and scalability issues. This chapter provides a detailed analysis of innovative research solutions for characterization of Synthetic Traffic Models, Graph Theoretical Analysis, methodologies for Task Mapping for System on Chip (SoC) Applications, illustration of the potential of the OMNeT++ Simulation Framework and a case study illustration of all those solutions integrated for the study of the STM Spidergon NoC architecture.
Multi-Core Embedded Systems
201
242
Bononi L.; Concer N.; Grammatikakis M.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11585/88816
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