TCAD solutions for increasing dimensionality in solid-state device and process simulations

The International Technology Roadmap for semiconductors (ITRS) indicates TCAD as one of the enabling methodologies that can support advance of technology progress at the remarkable pace of Moore's Law, by reducing development cycle times and costs in semiconductor industry. Several issues classified by the ITRS as difficult TCAD challenges reflect a general trend that we could name as increasing problem dimensionality. To overcome scaling limits of planar CMOS technology, a large variety of new device architectures has been proposed in recent years, whose operation is based on essentially three-dimensional effects. As a result, 3D simulations become a mandatory need for everyday tasks. The outlined scenario highlights the need for meshing tools able to represent complex 3D geometries in an accurate yet efficient way, resolving all critical features of the device structure without unacceptable drawbacks in terms of grid size. Process and device simulations also require completely automated gridding procedures to provide a suitable mesh adaptation to geometry or solution changes while avoiding artifacts or spurious effects. Besides, TCAD must contribute to the assessment and minimization of process variation effects, which become increasingly critical with device shrinking into the deca-nanometer range. Phenomena such as line-edge roughness and random dopant fluctuations broaden the device parameters distribution, thus requiring statistical treatment. This results in a computationally challenging 4D problem, where the additional dimension is the size of the considered ensemble. The aim of this work is to present multi-disciplinary approaches to handle the increasing problem dimensionality in a numerical simulation perspective. Particular emphasis will be placed in automatic meshing techniques for semiconductor devices. After reviewing theoretical and computational aspects of the main existing methods, a recently developed adaptive approach will be presented, based on advanced concepts from the multiresolution analysis and implemented exploiting efficient and fast algorithms from signal processing. The topic of variability estimation will also be analyzed, describing the most common techniques adopted for a realistic representation of analyzed random fluctuations and discussing how to improve the trade-off between the ensemble size allowed by computational constraints and confidence on statistical results. The proposed strategies can boost feasibility of the difficult bridge between nanoscale and chip-level design, improving efficiency of process/device simulation of small critical areas and allowing for accurate extraction of SPICE-level parameters and relative variations, a very important topic in a hierarchical simulation perspective.