Variability and its implications for FinFET SRAM

While traditional scaling used to be accompanied by an improvement in device performance, this is much more challenging in sub-100 nm technology generations, causing an inefficient scaling of transistor dimensions and circuit supply voltage. Leakage and variability in devices approaching the atomic scale are major limiting factors for continued employment of conventional CMOS technology. Three-dimensional architectures ensuring a tighter electrostatic control over the channel have potential to mitigate the outlined issues. By choosing a proper combination of high-Κ and metallic materials for the gate stack, it is possible to (i) resume a healthy trend of channel length scaling, (ii) limit gate leakage and (iii) set the device threshold voltage without recurring to increased channel doping. The use of undoped channels in multiple-gate structures such as FinFET significantly reduces the impact of random dopant fluctuations, which represent the major contribution to variability in planar bulk architectures. On the other hand, increased process complexity due to the intrinsic 3D nature of FinFETs is reflected in a significant impact of geometry fluctuations. Line-edge roughness (LER) of the fin, top- and sidewallgates is expected to be the dominant source of fluctuations in these devices. Physical-level models for LER will therefore be discussed and applied to estimate the impact of the roughness on the FinFET electrical performance. An ensemble Monte Carlo (MC) approach involving both 2D and 3D simulations will be presented, which allows assessing the relative importance of different LER components at the 32 nmtechnology node. The dependence of gate- LER issues on doping profiles will also be addressed, thus pointing out the key role of extensions for the FinFET performance and variability. A correlation-based approach for variability estimation will be described and compared to extensive MC simulations as well as to a simplistic sensitivity analysis in order to optimize the tradeoff between computational effort and statistical confidence. This analysis also allows identifying asymmetries in the device sensitivity to local geometry constrictions in different fin regions, thus further elucidating the impact of the parasitic extension resistance. FinFET is a promising candidate for future low-voltage/lowpower circuit applications. Six-transistor (6-T) SRAM will be considered as a benchmark to evaluate the impact of line-edge roughness at the circuit level. Stability of FinFET-based SRAMs in the hold, read and write operating modes will be evaluated taking into account several design options, namely cell sizing, crystal orientation and gate stack. VDD scalability of these cells will be assessed, based on mixed-mode simulations and comparison with measured data. Besides demonstrating a bottom-up methodology for variability prediction, the presented analysis thus provides design guidelines at the device and circuit level for mainstream applications of FinFETs in sub-40 nm technology generations.