Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as technology scales down in geometry and chips scale up in complexity, NoCs become the essential element to achieve the desired levels of performance and quality of service while curbing power consumption levels. Design and timing closure can only be achieved by a sophisticated set of tools that address NoC synthesis, optimization and validation.
Networks on Chips: From research to products / De Micheli G. ; Seiculescu C. ; Murali S. ; Benini L. ; Angiolini F. ; Pullini A.. - STAMPA. - (2010), pp. 300-305. (Intervento presentato al convegno Design Automation Conference (DAC), 2010 47th ACM/IEEE tenutosi a Anaheim, CA (USA) nel 13-18 June 2010).
Networks on Chips: From research to products
BENINI, LUCA;ANGIOLINI, FEDERICO;
2010
Abstract
Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as technology scales down in geometry and chips scale up in complexity, NoCs become the essential element to achieve the desired levels of performance and quality of service while curbing power consumption levels. Design and timing closure can only be achieved by a sophisticated set of tools that address NoC synthesis, optimization and validation.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
