3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks

Three-dimensional integrated circuits are a promising approach to push beyond the integration issues and IO bottlenecks of current Systems on Chips (SoCs). Designing the system interconnect for SoCs with many cores is already a challenge for conventional 2D ICs. The degree of freedom offered by the third dimension makes system interconnect design even more complicated and requires a scalable and predictable architecture for the interconnect, in order to achieve design closure. Networks on Chip (NoCs) was presented as a scalable and predictable architecture for system interconnect and therefore is a necessity for 3D integration. Designing an efficient NoC fabric that satisfies performance requirements, but also meets the constraints imposed by 3D technology, is a significant challenge. In this chapter, we move from an overview of communication requirements for current and future SoC platforms, and we analyze through-silicon-via (TSV) vertical interconnection technology, which is emerging as the most promising technology enabler for 3D integration. We then present methodologies and tools for automated 3D interconnect design, focusing on application-specific NoC synthesis for 3D ICs. 3D-NoC synthesis consists of finding the best NoC topology for the application, computing paths for the communication flows, assigning network components on to the layers of the 3D stack, and placing them in each layer. Experiments, performed on several SoC benchmarks demonstrate that 3D-NoCs with application specific tuning bring significant advantages in communication efficiency, power and delay.