A prototype of a 3D ASIC built up of a fast readout architecture, with sparsification capabilities, which interfaces with a matrix of a 256-pixel sensor, was recently submitted. The chosen technology is CMOS Chartered 130 nm as it is compatible with the Tezzaron facility to interconnect face-to-face two silicon wafers allowing for a vertical integration structure by means of through-silicon-vias. Particularly, the readout logic uses one layer that will be stacked on a sensor layer at the end of the fabrication process.
Fast readout logic interfacing a 256-pixel matrix of a dual-layer 3D device / A. Gabrielli; F. Giorgi; M Villa; F. Morsani. - In: JOURNAL OF INSTRUMENTATION. - ISSN 1748-0221. - ELETTRONICO. - 5:(2010), pp. c07005-c07005-5. (Intervento presentato al convegno Workshop on Intelligent Trackers 2010 tenutosi a Berkeley (CA) nel 3 - 5 February 2010) [10.1088/1748-0221/5/07/C07005].
Fast readout logic interfacing a 256-pixel matrix of a dual-layer 3D device
GABRIELLI, ALESSANDRO;GIORGI, FILIPPO MARIA;VILLA, MAURO;
2010
Abstract
A prototype of a 3D ASIC built up of a fast readout architecture, with sparsification capabilities, which interfaces with a matrix of a 256-pixel sensor, was recently submitted. The chosen technology is CMOS Chartered 130 nm as it is compatible with the Tezzaron facility to interconnect face-to-face two silicon wafers allowing for a vertical integration structure by means of through-silicon-vias. Particularly, the readout logic uses one layer that will be stacked on a sensor layer at the end of the fabrication process.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
