Several recent works have shown the advantages of using phase-change memory (PCM) in developing brain-inspired computing approaches. In particular, PCM cells have been applied to the direct computation of matrix-vector multiplications in the analog domain. However, the intrinsic nonlinearity of these cells with respect to the applied voltage is detrimental. In this paper we consider a PCM array as the encoder in a Compressed Sensing (CS) acquisition system, and investigate the effect of the non-linearity of the cells. We introduce a CS decoding strategy that is able to compensate for PCM nonlinearities by means of an iterative approach. At each step, the current signal estimate is used to approximate the average behaviour of the PCM cells used in the encoder. Monte Carlo simulations relying on a PCM model extracted from an STMicrolectronics 90 nm BCD chip validate the performance of the algorithm with various degrees of nonlinearities, showing up to 35 dB increase in median performance as compared to standard decoding procedures.

Compressed sensing by phase change memories: Coping with encoder non-linearities

Antolini Alessio;Mangia Mauro;Rovatti Riccardo;Franchi Scarselli Eleonora;Gnudi Antonio;
2021

Abstract

Several recent works have shown the advantages of using phase-change memory (PCM) in developing brain-inspired computing approaches. In particular, PCM cells have been applied to the direct computation of matrix-vector multiplications in the analog domain. However, the intrinsic nonlinearity of these cells with respect to the applied voltage is detrimental. In this paper we consider a PCM array as the encoder in a Compressed Sensing (CS) acquisition system, and investigate the effect of the non-linearity of the cells. We introduce a CS decoding strategy that is able to compensate for PCM nonlinearities by means of an iterative approach. At each step, the current signal estimate is used to approximate the average behaviour of the PCM cells used in the encoder. Monte Carlo simulations relying on a PCM model extracted from an STMicrolectronics 90 nm BCD chip validate the performance of the algorithm with various degrees of nonlinearities, showing up to 35 dB increase in median performance as compared to standard decoding procedures.
Proceedings - IEEE International Symposium on Circuits and Systems
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Paolino Carmine, Antolini Alessio, Pareschi Fabio, Mangia Mauro, Rovatti Riccardo, Franchi Scarselli Eleonora, Gnudi Antonio, Setti Gianluca, Canegallo Roberto, Carissimi Marcella, Pasotti Marco
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11585/860988
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