In deep submicron designs of MultiProcessor Systems-on-Chip (MPSoC) architectures, uncompensated within-die process variations and aging effects will lead to an increasing uncertainty and unbalancing of expected core lifetimes. In this paper we present an adaptive workload allocation strategy for run-time compensation of variations- and aging-induced unbalanced core lifetimes by means of core activity duty cycling. The proposed techniques regulates the percentage of idle time on short-expected-life cores to meet the platform lifetime target with minimum performance degradation. Experiments have been conducted on a multiprocessor simulator of a next-generation industrial MPSoC platform for multimedia applications made of a general purpose processor and programmable accelerators.
Adaptive idleness distribution for non-uniform aging tolerance in MultiProcessor Systems-on-Chip / Paterna F.; Benini L.; Acquaviva A.; Papariello F.; Desoli G.; Olivieri M.. - STAMPA. - (2009), pp. 906-909. (Intervento presentato al convegno Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09 tenutosi a Nice, France nel 20-24 April 2009).
Adaptive idleness distribution for non-uniform aging tolerance in MultiProcessor Systems-on-Chip
PATERNA, FRANCESCO;BENINI, LUCA;ACQUAVIVA, ANDREA;
2009
Abstract
In deep submicron designs of MultiProcessor Systems-on-Chip (MPSoC) architectures, uncompensated within-die process variations and aging effects will lead to an increasing uncertainty and unbalancing of expected core lifetimes. In this paper we present an adaptive workload allocation strategy for run-time compensation of variations- and aging-induced unbalanced core lifetimes by means of core activity duty cycling. The proposed techniques regulates the percentage of idle time on short-expected-life cores to meet the platform lifetime target with minimum performance degradation. Experiments have been conducted on a multiprocessor simulator of a next-generation industrial MPSoC platform for multimedia applications made of a general purpose processor and programmable accelerators.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.