In September 2008 the Slim5 collaboration submitted a low material budget silicon demonstrator to test with 12 GeV/c protons, at the PS-T9 test-beam at CERN. The beam test setup was composed of two different detectors (DUTs) placed inside a reference microstrip silicon tracker telescope. The first was a 4k-Pixel Matrix of Deep N Well MAPS, developed in a 130 Nm CMOS Technology, providing digital sparsified readout. The other one was a high resistivity double sided silicon detector, with short strips at 45 angle to the detector's edge, read out by FSSR2 chips. In total, the set-up contained 38 chips for 12k individual electronic channels. The data acquisition of the experiment was done by means of two high bandwidth, fully programmable 9U VME board (EDRO) that have been designed to stand a 12 Gbit/s input rate, 1.2 Gbit/s output rate and have the possibility to perform different types of trigger strategies on data. The most important one was the on-line track identification performed with the help of an Associative Memory board, which demonstrated the capability of the setup to trigger on identified tracks with a minimal latency (< 1 us). In the contribution, the beam test setup, the data acquisition and trigger systems are presented. The main remarkable trigger and data acquisition performances (2.5 MHz event evaluation rate, 40 kHz data acquisition rate, event selection on identified tracks) that lead to a successful data taking are discussed.
The L1 Track Trigger and High Data Rate Acquisition System for the SLIM5 Beam Test
VILLA, MAURO
2009
Abstract
In September 2008 the Slim5 collaboration submitted a low material budget silicon demonstrator to test with 12 GeV/c protons, at the PS-T9 test-beam at CERN. The beam test setup was composed of two different detectors (DUTs) placed inside a reference microstrip silicon tracker telescope. The first was a 4k-Pixel Matrix of Deep N Well MAPS, developed in a 130 Nm CMOS Technology, providing digital sparsified readout. The other one was a high resistivity double sided silicon detector, with short strips at 45 angle to the detector's edge, read out by FSSR2 chips. In total, the set-up contained 38 chips for 12k individual electronic channels. The data acquisition of the experiment was done by means of two high bandwidth, fully programmable 9U VME board (EDRO) that have been designed to stand a 12 Gbit/s input rate, 1.2 Gbit/s output rate and have the possibility to perform different types of trigger strategies on data. The most important one was the on-line track identification performed with the help of an Associative Memory board, which demonstrated the capability of the setup to trigger on identified tracks with a minimal latency (< 1 us). In the contribution, the beam test setup, the data acquisition and trigger systems are presented. The main remarkable trigger and data acquisition performances (2.5 MHz event evaluation rate, 40 kHz data acquisition rate, event selection on identified tracks) that lead to a successful data taking are discussed.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
