Investigation on saturation effects in the rugged LDMOS transistor

A numerical investigation on the behavior of the rugged LDMOS transistor operating in the high current-voltage pulsed regime is carried out with the aim of clarifying the physical origin of the drain-current “enhancement” visible in the output characteristics at high drain and gate biases. The socalled “quasi-saturation” effect and the current enhancement are explained in terms of the strong nonlinear behavior of the drift resistance, which is heavily affected by the carrier velocity saturation and by the impact-generated electron-hole pairs. At high gate and drain voltages, the reduction of the drift resistance caused by the latter effect raises the electrostatic potential near the channel end and drives herewith the intrinsic MOSFET into a second saturation condition.