Heterogeneous SoCs (HeSoCs) typically share a single DRAM between the CPU and GPU, making workloads susceptible to memory interference, and predictable execution troublesome. State-of-the art predictable execution models (PREM) for HeSoCs prefetch data to the GPU scratchpad memory (SPM), for computations to be insensitive to CPU-generated DRAM traffic. However, the amount of work that the small SPM sizes allow is typically insufficient to absorb CPU/GPU synchronization costs. On-chip caches are larger, and would solve this issue, but have been argued too unpredictable due to self-evictions. We show how self-eviction can be minimized in GPU caches via clever managing of prefetches, thus lowering the performance cost, while retaining timing predictability.
Taming Data Caches for Predictable Execution on GPU-based SoCs / Forsberg B.; Benini L.; Marongiu A.. - ELETTRONICO. - (2019), pp. 8715255.650-8715255.653. (Intervento presentato al convegno 22nd Design, Automation and Test in Europe Conference and Exhibition, DATE 2019 tenutosi a Firenze nel 2019, 25-29 of March) [10.23919/DATE.2019.8715255].
Taming Data Caches for Predictable Execution on GPU-based SoCs
Benini L.;
2019
Abstract
Heterogeneous SoCs (HeSoCs) typically share a single DRAM between the CPU and GPU, making workloads susceptible to memory interference, and predictable execution troublesome. State-of-the art predictable execution models (PREM) for HeSoCs prefetch data to the GPU scratchpad memory (SPM), for computations to be insensitive to CPU-generated DRAM traffic. However, the amount of work that the small SPM sizes allow is typically insufficient to absorb CPU/GPU synchronization costs. On-chip caches are larger, and would solve this issue, but have been argued too unpredictable due to self-evictions. We show how self-eviction can be minimized in GPU caches via clever managing of prefetches, thus lowering the performance cost, while retaining timing predictability.File | Dimensione | Formato | |
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Taming_data_caches.pdf
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