This paper investigates the digital circuit-level performance of an inverter realised with n- and p-type tunnel field-effect transistors (TFETs) integrated on the same InAs/Al0.05Ga0.95Sb tech nology platform in the presence of interface traps and localized strain. The TFET-based inverter is simulated for two different IOFF values, namely 100 nA/μm and 10 pA/μm to target both high-performance and low-power applications. Based on 3D full-quantum simulations, interface traps induce a significant degradation of the voltage gain, noise margin and transient performance despite the better subthreshold slope. The effect of localized strain at the source/channel heterojunction caused by lattice mismatch, while being beneficial in terms of on-current, is unable to recover the circuit-level performance of the ideal case. The device with traps and localized strain is able to outperform the ideal one only in terms of switching transients for IOFF=10 pA/μm.
TFET inverter static and transient performances in presence of traps and localized strain / Gnani E.; Visciarelli M.; Gnudi A.; Reggiani S.; Baccarani G.. - In: SOLID-STATE ELECTRONICS. - ISSN 0038-1101. - ELETTRONICO. - 159:(2019), pp. 38-42. [10.1016/j.sse.2019.03.051]
TFET inverter static and transient performances in presence of traps and localized strain
Gnani E.
;Visciarelli M.;Gnudi A.;Reggiani S.;Baccarani G.
2019
Abstract
This paper investigates the digital circuit-level performance of an inverter realised with n- and p-type tunnel field-effect transistors (TFETs) integrated on the same InAs/Al0.05Ga0.95Sb tech nology platform in the presence of interface traps and localized strain. The TFET-based inverter is simulated for two different IOFF values, namely 100 nA/μm and 10 pA/μm to target both high-performance and low-power applications. Based on 3D full-quantum simulations, interface traps induce a significant degradation of the voltage gain, noise margin and transient performance despite the better subthreshold slope. The effect of localized strain at the source/channel heterojunction caused by lattice mismatch, while being beneficial in terms of on-current, is unable to recover the circuit-level performance of the ideal case. The device with traps and localized strain is able to outperform the ideal one only in terms of switching transients for IOFF=10 pA/μm.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
