In this paper we analyze the effect of the Bias Temperature Instability (BTI) aging phenomenon on the delay of deskew buffers employed in high performance microprocessors. Our analysis shows that, during circuit lifetime, the delay induced by BTI on each deskew buffer within the microprocessor can be significantly different, depending on how each deskew buffer is configured after fabrication (to compensate clock skews occurring during the fabrication process) and the operating temperature. Therefore, we show that even if deskew buffers compensate skews among clock signals after fabrication, their different level of degradation during circuit lifetime can generate significant skews between clock signals after only some month of circuit operation in the field. Moreover, the variations in the delay of deskew buffers due to BTI can exceed the maximum compensation range enabled by such schemes, thus making skew compensation during circuit lifetime ineffective. Finally, we propose a simple mathematical model enabling to estimate the maximum skew among clock signals during the chip lifetime. The model can be used to activate proactive compensation approaches (e.g., clock frequency reduction) allowing to avoid malfunctions caused by an excessive skew among clock signals generated by BTI degradation of the deskew buffers.

Impact of Bias Temperature Instability (BTI) Aging Phenomenon on Clock Deskew Buffers

M. Omaña
2019

Abstract

In this paper we analyze the effect of the Bias Temperature Instability (BTI) aging phenomenon on the delay of deskew buffers employed in high performance microprocessors. Our analysis shows that, during circuit lifetime, the delay induced by BTI on each deskew buffer within the microprocessor can be significantly different, depending on how each deskew buffer is configured after fabrication (to compensate clock skews occurring during the fabrication process) and the operating temperature. Therefore, we show that even if deskew buffers compensate skews among clock signals after fabrication, their different level of degradation during circuit lifetime can generate significant skews between clock signals after only some month of circuit operation in the field. Moreover, the variations in the delay of deskew buffers due to BTI can exceed the maximum compensation range enabled by such schemes, thus making skew compensation during circuit lifetime ineffective. Finally, we propose a simple mathematical model enabling to estimate the maximum skew among clock signals during the chip lifetime. The model can be used to activate proactive compensation approaches (e.g., clock frequency reduction) allowing to avoid malfunctions caused by an excessive skew among clock signals generated by BTI degradation of the deskew buffers.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11585/694714
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