This work intends to briefly overview the new technological updates on the LHC ATLAS acquisition system of the Pixel Detector. The herein presented Read-Out Driver (ROD) is a VME board devoted to data processing, configuration and control. It is designed to provide data formatting, front-end specific error handling, and calibration. This board was initially designed to interface the data sensed by the Insertable B-Layer (IBL) with the ATLAS Trigger and Data AcQuisition (TDAQ) system. IBL is the innermost sensing layer of the ATLAS Pixel Detector, added during the 2013/2014 LHC long shutdown, to withstand higher luminosity and feature higher throughput performance. To readout the new layer of pixels, with a smaller pixel size with respect to the other outer layers, a front end ASIC (FE-I4) was designed. Because of its optimal performance, it was decided to adopt the IBL ROD also for Pixel Layer 1 and Layer 2. Among the several advantages, one of the most important is the reduction of link occupancy due to the increased bandwidth (80 Mb/s, two times the previous one). 40 ROD boards, fabricated and tested in 2015, were installed in the Layer 2 acquisition system featuring outstanding performance while 45 RODs for Layer 1 are still under test and will be installed by the end of 2016.

New updates on the ATLAS ROD board implementation for Pixel Layer 1 and Layer 2

Giangiacomi, Nico;Balbi, Gabriele;Gabrielli, Alessandro;
2018

Abstract

This work intends to briefly overview the new technological updates on the LHC ATLAS acquisition system of the Pixel Detector. The herein presented Read-Out Driver (ROD) is a VME board devoted to data processing, configuration and control. It is designed to provide data formatting, front-end specific error handling, and calibration. This board was initially designed to interface the data sensed by the Insertable B-Layer (IBL) with the ATLAS Trigger and Data AcQuisition (TDAQ) system. IBL is the innermost sensing layer of the ATLAS Pixel Detector, added during the 2013/2014 LHC long shutdown, to withstand higher luminosity and feature higher throughput performance. To readout the new layer of pixels, with a smaller pixel size with respect to the other outer layers, a front end ASIC (FE-I4) was designed. Because of its optimal performance, it was decided to adopt the IBL ROD also for Pixel Layer 1 and Layer 2. Among the several advantages, one of the most important is the reduction of link occupancy due to the increased bandwidth (80 Mb/s, two times the previous one). 40 ROD boards, fabricated and tested in 2015, were installed in the Layer 2 acquisition system featuring outstanding performance while 45 RODs for Layer 1 are still under test and will be installed by the end of 2016.
Giangiacomi, Nico; Balbi, Gabriele; Damilano, Alessia; Falchieri, Davide; Gabrielli, Alessandro; Lama, Luca; Travaglini, Riccardo
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11585/642002
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