In this paper, we present an analysis of the degradation induced by hot-carrier stress in new generation power lateral double-diffused MOS (LDMOS) transistors. Two architectures with the same nominal voltage and comparable performance featuring a selective LOCOS and a shallow-trench isolation are investigated by means of constant voltage stress measurements and TCAD simulations. In particular, the on-resistance degradation in linear regime is experimentally extracted and numerically reproduced under different stress conditions. A similar amount of degradation has been reached by the two architectures, although different physical mechanisms contribute to the creation of the interface states. By using a recently developed physics-based degradation model, it has been possible to distinguish the damage due to collisions of single high-energetic electrons (single-particle events) and the contribution of colder electrons impinging on the silicon/oxide interface (multiple-particle events). A clear dominance of the single-electron collisions has been found in the case of LOCOS structure, whereas the multiple-particle effect plays a clear role in STI-based device at larger gate-voltage stress.
Hot-Carrier Degradation in Power LDMOS: Selective LOCOS-Versus STI-Based Architecture / Tallarico, Andrea Natale*; Reggiani, Susanna; Depetro, Riccardo; Torti, Andrea Mario; Croce, Giuseppe; Sangiorgi, Enrico; Fiegna, Claudio. - In: IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY. - ISSN 2168-6734. - ELETTRONICO. - 6:1(2018), pp. 8255610.219-8255610.226. [10.1109/JEDS.2018.2792539]
Hot-Carrier Degradation in Power LDMOS: Selective LOCOS-Versus STI-Based Architecture
Tallarico, Andrea Natale
;Reggiani, Susanna;Sangiorgi, Enrico;Fiegna, Claudio
2018
Abstract
In this paper, we present an analysis of the degradation induced by hot-carrier stress in new generation power lateral double-diffused MOS (LDMOS) transistors. Two architectures with the same nominal voltage and comparable performance featuring a selective LOCOS and a shallow-trench isolation are investigated by means of constant voltage stress measurements and TCAD simulations. In particular, the on-resistance degradation in linear regime is experimentally extracted and numerically reproduced under different stress conditions. A similar amount of degradation has been reached by the two architectures, although different physical mechanisms contribute to the creation of the interface states. By using a recently developed physics-based degradation model, it has been possible to distinguish the damage due to collisions of single high-energetic electrons (single-particle events) and the contribution of colder electrons impinging on the silicon/oxide interface (multiple-particle events). A clear dominance of the single-electron collisions has been found in the case of LOCOS structure, whereas the multiple-particle effect plays a clear role in STI-based device at larger gate-voltage stress.File | Dimensione | Formato | |
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