Reconfigurable architectures provide the user the capability to couple performance typical of hardware design with the flexibility of the software. This paper presents the design of AES/Rijndael on a dynamically reconfigurable architecture. A performance improvement of three order of magnitude was shown compared to the reference code and up to 24times speed-up figure wrt fast C implementations over a RISC processor. A maximum throughput of 546 Mbit/sec is achieved. Compared to prior art, a better energy efficiency with respect to the other programmable solutions was shown, obtaining up to 3 Mbit/sec/mW
Implementation of AES/Rijndael on a dynamically reconfigurable architecture / C.Mucci; L.Vanzolini; F.Campi; A.Lodi; A.Deledda; M.Toma; R.Guerrieri. - STAMPA. - (2007), pp. 1-6. (Intervento presentato al convegno Design, Automation and Test in Europe Conference and Exhibition (DATE '07) tenutosi a Nice, France nel 16-20 Apr.2007).
Implementation of AES/Rijndael on a dynamically reconfigurable architecture
MUCCI, CLAUDIO;CAMPI, FABIO;LODI, ANDREA;DELEDDA, ANTONIO;TOMA, MARIO;GUERRIERI, ROBERTO
2007
Abstract
Reconfigurable architectures provide the user the capability to couple performance typical of hardware design with the flexibility of the software. This paper presents the design of AES/Rijndael on a dynamically reconfigurable architecture. A performance improvement of three order of magnitude was shown compared to the reference code and up to 24times speed-up figure wrt fast C implementations over a RISC processor. A maximum throughput of 546 Mbit/sec is achieved. Compared to prior art, a better energy efficiency with respect to the other programmable solutions was shown, obtaining up to 3 Mbit/sec/mWI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
