In this paper, we show that clock faults producing duty-cycle variations, which have been proven very likely, can give rise to min or max delay violations. This mandates new, specific testing approaches for clock faults, to avoid them to compromise the system correct operation in the field, with dramatic effects on product quality and defect level. We then introduce a new scheme that can be employed to detect the clock faults causing duty-cycle variations.
Clock Faults Induced Min and Max Delay Violations / D. Rossi; M. Omaña; J. M. Cazeaux; C. Metra; TM. Mak. - In: JOURNAL OF ELECTRONIC TESTING. - ISSN 0923-8174. - STAMPA. - 30:1(2014), pp. 111-123. [10.1007/s10836-013-5426-4]
Clock Faults Induced Min and Max Delay Violations
ROSSI, DANIELE;OMANA, MARTIN EUGENIO;METRA, CECILIA;
2014
Abstract
In this paper, we show that clock faults producing duty-cycle variations, which have been proven very likely, can give rise to min or max delay violations. This mandates new, specific testing approaches for clock faults, to avoid them to compromise the system correct operation in the field, with dramatic effects on product quality and defect level. We then introduce a new scheme that can be employed to detect the clock faults causing duty-cycle variations.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
