The chip prototype Apsel4well, including monolithic active pixel sensors (MAPS), is meant as an upgrade solution for the Layer0 of the SuperB silicon vertex tracker. The design is based on a 180 nm CMOS process with quadruple well called INMAPS. This technology makes it possible to overcome the main drawbacks of three transistor MAPS. Moreover, the presence of a high resistivity epitaxial layer is expected to lead to a further improvement in terms of charge collection performance and radiation resistance. This work introduces the channel readout design features of the chip Apsel4well developed with the mentioned approach and shows results of device simulations of a 3×3 pixel matrix.
A quadruple well CMOS MAPS prototype for the Layer0 of the SuperB SVT
GABRIELLI, ALESSANDRO;GIORGI, FILIPPO MARIA
2013
Abstract
The chip prototype Apsel4well, including monolithic active pixel sensors (MAPS), is meant as an upgrade solution for the Layer0 of the SuperB silicon vertex tracker. The design is based on a 180 nm CMOS process with quadruple well called INMAPS. This technology makes it possible to overcome the main drawbacks of three transistor MAPS. Moreover, the presence of a high resistivity epitaxial layer is expected to lead to a further improvement in terms of charge collection performance and radiation resistance. This work introduces the channel readout design features of the chip Apsel4well developed with the mentioned approach and shows results of device simulations of a 3×3 pixel matrix.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
