An 8 bit segmented current steering DAC is presented for the compensation of mismatch of sensors with current output arranged in a large arrays. The DAC is implemented in a 1.8V supply voltage 180nm standard CMOS technology. Post layout simulations reveal that the design target concerning a sampling frequency of 2.6MHz is exceeded, worst-case settling time equals 60.6 ns. The output current range is 0–10μA, which translates into an LSB of 40nA. Good linearity is achieved, INL<0.5LSB and DNL < 0.4 LSB, respectively. Static power consumption with the outputs operated at a voltage of 0.9 V is approximately 10μW. Dynamic power, mainly consumed by switching activity of the digital circuit parts, amounts to 100 uW at 2.6 MHz operation frequency. Total area is 38.6 um x 2933um.
An 8 bit current steering DAC for offset compensation purposes in sensor arrays
FRANCHI SCARSELLI, ELEONORA;
2012
Abstract
An 8 bit segmented current steering DAC is presented for the compensation of mismatch of sensors with current output arranged in a large arrays. The DAC is implemented in a 1.8V supply voltage 180nm standard CMOS technology. Post layout simulations reveal that the design target concerning a sampling frequency of 2.6MHz is exceeded, worst-case settling time equals 60.6 ns. The output current range is 0–10μA, which translates into an LSB of 40nA. Good linearity is achieved, INL<0.5LSB and DNL < 0.4 LSB, respectively. Static power consumption with the outputs operated at a voltage of 0.9 V is approximately 10μW. Dynamic power, mainly consumed by switching activity of the digital circuit parts, amounts to 100 uW at 2.6 MHz operation frequency. Total area is 38.6 um x 2933um.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
