The physical behavior of the dual N/P-LDMOS device concept is reviewed and analyzed. Through a proper optimization, a scalable device with good RSP vs. VBD performance in a range of 20–150 V is identified. Further, the current expansion at high gate and drain biases is fully explained by means of TCAD simulations and nicely exploited for the design of an LDO linear voltage regulator with excellent performance in terms of both drop-out voltage and maximum load current.
TCAD optimization of a dual N/P-LDMOS transistor / S. Poli; S. Reggiani; R. K. Sharma; G. Baccarani; E. Gnani; A. Gnudi; M. Denison. - STAMPA. - (2011), pp. 247-250. (Intervento presentato al convegno (ESSDERC 2011) tenutosi a Helsinki nel 13-15 September 2011) [10.1109/ESSDERC.2011.6044188].
TCAD optimization of a dual N/P-LDMOS transistor
POLI, STEFANO;REGGIANI, SUSANNA;BACCARANI, GIORGIO;GNANI, ELENA;GNUDI, ANTONIO;
2011
Abstract
The physical behavior of the dual N/P-LDMOS device concept is reviewed and analyzed. Through a proper optimization, a scalable device with good RSP vs. VBD performance in a range of 20–150 V is identified. Further, the current expansion at high gate and drain biases is fully explained by means of TCAD simulations and nicely exploited for the design of an LDO linear voltage regulator with excellent performance in terms of both drop-out voltage and maximum load current.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
