Sfoglia per Autore
Scalability Analysis of Evolving SoC Interconnect Protocols
2004 M. Ruggiero;F. Angiolini;F. Poletti;D. Bertozzi;L. Benini;R. Zafalon
A Post-Compiler Approach to Scratchpad Mapping of Code
2004 F. Angiolini;F. Menichelli;A. Ferrero;L. Benini;M. Olivieri
Analyzing On-Chip Communication in a MPSoC Environment
2004 M. Loghi;F. Angiolini;D. Bertozzi;L. Benini;R. Zafalon
Fault Tolerance Overhead in Network-on-Chip Flow Control Schemes
2005 A. Pullini;F. Angiolini;D. Bertozzi;L. Benini
Simultaneous Memory and Bus Partitioning for SoC Architectures
2005 S. Srinivasan;F. Angiolini;M. Ruggiero;N. Vijaykrishnan;L. Benini
xpipes Lite: A Synthesis Oriented Design Flow For Networks on Chips
2005 S. Stergiou; F. Angiolini; S. Carta; L. Raffo; D. Bertozzi; G. De Micheli
Realistically Rendering SoC Traffic Patterns with Interrupt Awareness
2005 S. Mahadevan;F. Angiolini;J. Madsen;L. Benini;J. Sparsø
An Efficient Profile-Based Algorithm for Scratchpad Memory Partitioning
2005 F. Angiolini; L. Benini; A. Caprara
Contrasting a NoC and a traditional interconnect fabric with layout awareness
2006 F. Angiolini; P. Meloni; S. Carta; L. Benini; L. Raffo
Reliability Support for On-Chip Memories Using Networks-on-Chip
2006 F. Angiolini; D. Atienza; S. Murali; L. Benini; G. De Micheli
Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips
2006 S. Murali; P. Meloni; F. Angiolini; D. Atienza; S. Carta; L. Benini; G. De Micheli; L. Raffo
An integrated open framework for heterogeneous MPSoC design space exploration
2006 F. Angiolini; J. Ceng; R. Leupers; F. Ferrari; C. Ferri; L. Benini
Networks on Chips: A Synthesis Perspective
2006 F. Angiolini; P. Meloni; D. Bertozzi; L. Benini; S. Carta; L. Raffo
Designing Application-Specific Networks on Chips with Floorplan Information
2006 S. Murali; P. Meloni; F. Angiolini; D. Atienza; S. Carta; L. Benini; G. De Micheli
Diseño de redes en chip de propósito específico con información de rutado físico
2006 D. Atienza; S. Murali; F. Angiolini; L. Benini; G. De Micheli; J.M. Mendias; R. Hermida
Comparison of a Timing-Error Tolerant Scheme with a traditional Re-transmission Mechanism for Networks on Chips
2006 S. Murali; R. Tamhankar; F. Angiolini; A. Pullini; D. Atienza; L. Benini; G. De Micheli
Area and Power Modeling for Networks-on-Chip with Layout Awareness
2007 P. Meloni; I. Loi; F. Angiolini; S. Carta; M. Barbaro; L. Raffo; L. Benini
NoC Design and Implementation in 65 nm Technology
2007 A. Pullini; F. Angiolini; P. Meloni; D. Atienza; S. Murali; L. Raffo; G. De Micheli; L. Benini;
Improving the Fault Tolerance of Nanometric PLA Designs
2007 F. Angiolini; H. Ben Jamaa; D. Atienza; L. Benini; G. De Micheli
Networks-on-Chip: From Idea to Implementation
2007 F. Angiolini; L. Benini
| Titolo | Autore(i) | Anno | Periodico | Editore | Tipo | File |
|---|---|---|---|---|---|---|
| Scalability Analysis of Evolving SoC Interconnect Protocols | M. Ruggiero;F. Angiolini;F. Poletti;D. Bertozzi;L. Benini;R. Zafalon | 2004-01-01 | - | s.n | 4.01 Contributo in Atti di convegno | - |
| A Post-Compiler Approach to Scratchpad Mapping of Code | F. Angiolini;F. Menichelli;A. Ferrero;L. Benini;M. Olivieri | 2004-01-01 | - | s.n | 4.01 Contributo in Atti di convegno | - |
| Analyzing On-Chip Communication in a MPSoC Environment | M. Loghi;F. Angiolini;D. Bertozzi;L. Benini;R. Zafalon | 2004-01-01 | - | s.n | 4.01 Contributo in Atti di convegno | - |
| Fault Tolerance Overhead in Network-on-Chip Flow Control Schemes | A. Pullini;F. Angiolini;D. Bertozzi;L. Benini | 2005-01-01 | - | s.n | 4.01 Contributo in Atti di convegno | - |
| Simultaneous Memory and Bus Partitioning for SoC Architectures | S. Srinivasan;F. Angiolini;M. Ruggiero;N. Vijaykrishnan;L. Benini | 2005-01-01 | - | s.n | 4.01 Contributo in Atti di convegno | - |
| xpipes Lite: A Synthesis Oriented Design Flow For Networks on Chips | S. Stergiou; F. Angiolini; S. Carta; L. Raffo; D. Bertozzi; G. De Micheli | 2005-01-01 | - | 2005 IEEE | 4.01 Contributo in Atti di convegno | - |
| Realistically Rendering SoC Traffic Patterns with Interrupt Awareness | S. Mahadevan;F. Angiolini;J. Madsen;L. Benini;J. Sparsø | 2005-01-01 | - | s.n | 4.01 Contributo in Atti di convegno | - |
| An Efficient Profile-Based Algorithm for Scratchpad Memory Partitioning | F. Angiolini; L. Benini; A. Caprara | 2005-01-01 | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - | 1.01 Articolo in rivista | - |
| Contrasting a NoC and a traditional interconnect fabric with layout awareness | F. Angiolini; P. Meloni; S. Carta; L. Benini; L. Raffo | 2006-01-01 | - | European Design and Automation Association | 4.01 Contributo in Atti di convegno | - |
| Reliability Support for On-Chip Memories Using Networks-on-Chip | F. Angiolini; D. Atienza; S. Murali; L. Benini; G. De Micheli | 2006-01-01 | - | s.n | 4.01 Contributo in Atti di convegno | - |
| Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips | S. Murali; P. Meloni; F. Angiolini; D. Atienza; S. Carta; L. Benini; G. De Micheli; L. Raffo | 2006-01-01 | - | s.n | 4.01 Contributo in Atti di convegno | - |
| An integrated open framework for heterogeneous MPSoC design space exploration | F. Angiolini; J. Ceng; R. Leupers; F. Ferrari; C. Ferri; L. Benini | 2006-01-01 | - | European Design and Automation Association | 4.01 Contributo in Atti di convegno | - |
| Networks on Chips: A Synthesis Perspective | F. Angiolini; P. Meloni; D. Bertozzi; L. Benini; S. Carta; L. Raffo | 2006-01-01 | - | John von Neumann Institute for Computing (NIC) | 4.01 Contributo in Atti di convegno | - |
| Designing Application-Specific Networks on Chips with Floorplan Information | S. Murali; P. Meloni; F. Angiolini; D. Atienza; S. Carta; L. Benini; G. De Micheli | 2006-01-01 | - | s.n | 4.01 Contributo in Atti di convegno | - |
| Diseño de redes en chip de propósito específico con información de rutado físico | D. Atienza; S. Murali; F. Angiolini; L. Benini; G. De Micheli; J.M. Mendias; R. Hermida | 2006-01-01 | - | s.n | 4.01 Contributo in Atti di convegno | - |
| Comparison of a Timing-Error Tolerant Scheme with a traditional Re-transmission Mechanism for Networks on Chips | S. Murali; R. Tamhankar; F. Angiolini; A. Pullini; D. Atienza; L. Benini; G. De Micheli | 2006-01-01 | - | s.n | 4.01 Contributo in Atti di convegno | - |
| Area and Power Modeling for Networks-on-Chip with Layout Awareness | P. Meloni; I. Loi; F. Angiolini; S. Carta; M. Barbaro; L. Raffo; L. Benini | 2007-01-01 | VLSI DESIGN | - | 1.01 Articolo in rivista | - |
| NoC Design and Implementation in 65 nm Technology | A. Pullini; F. Angiolini; P. Meloni; D. Atienza; S. Murali; L. Raffo; G. De Micheli; L. Benini; | 2007-01-01 | - | IEEE Circuits and Systems Society | 4.01 Contributo in Atti di convegno | - |
| Improving the Fault Tolerance of Nanometric PLA Designs | F. Angiolini; H. Ben Jamaa; D. Atienza; L. Benini; G. De Micheli | 2007-01-01 | - | s.n | 4.01 Contributo in Atti di convegno | - |
| Networks-on-Chip: From Idea to Implementation | F. Angiolini; L. Benini | 2007-01-01 | - | s.n | 4.02 Riassunto (Abstract) | - |
Legenda icone
- file ad accesso aperto
- file disponibili sulla rete interna
- file disponibili agli utenti autorizzati
- file disponibili solo agli amministratori
- file sotto embargo
- nessun file disponibile